The present invention relates to memory architectures, and particularly to the architecture of a row decoder for a so-called NAND-type ROM (Read Only Memory)..sup.1 FNT .sup.1 See Cuppens et al., "A 256 kbit ROM with Serial ROM Cell Structure," 18 IEEE JOURNAL OF SOLID-STATE CIRCUITS 340ff (June 1983); Kawagoe et al., "Minimum size ROM structure compatible with silicon-gate E/D MOS LSI,"11 IEEE JOURNAL OF SOLID-STATE CIRCUITS 360ff (June 1976); Momodori et al., "A 4-Mb NAND EEPROM with Tight [sic] Programmed V.sub.t Distributions," 26 IEEE JOURNAL OF SOLID-STATE CIRCUITS 492ff (April 1991); and U.S. Pat. Nos. 4,059,826, 4,142,176, 4,344,005, 4,419,741, 4,423,432, 4,480,320, 4,489,400, 4,565,712, 4,570,239, 4,646,265, 4,980,861, and 5,060,190; all of which are hereby incorporated by reference.
NAND-type ROMs use an architecture where all cells along a single column position are connected in series. Nonswitching cells (e.g. cells programmed to "1") are permanently ON, and other cells ("0" cells) turn on or off depending on the signal applied by a row line. Thus, to sense a particular row, the transistors of all other rows are turned on. Current will pass the bitline, and pull up a sensed node at the sense amplifier, only if all cells in the column are turned on. Since the cells of all other rows are certain to be on, the current signal seen at the sense amplifier (for any given column) will depend on the ON or OFF state of the cell in the selected row, in that column..sup.2 FNT .sup.2 In practice, the number of cells in series is limited, to avoid speed degradation due to the on-state series resistance of the transistors in the nonselected rows.
The advantage of this configuration is increased density, since no contacts are needed in the array. However, a different decoding architecture is needed. Moreover, a contactless array can impose tight constraints on the geometry of peripheral circuits.
One of the most difficult problems to be overcome when designing a ROM array, wherein memory cells are physically arranged in a matrix of rows and columns and are organized in a plurality of selectable NAND parcels of cells, is represented by the implementation of a decoder which will be compatible with the physical ordering "pitch" (i.e. the very small distance between adjacent rows of memory cells).
Moreover, for a matrix of cells organized in a NAND configuration, the decoding is necessarily a two-level decoding. This requires the decoder to be capable of driving in parallel all homonymous rows of all the NAND parcels of cells. This "second-level" decoding circuitry, suitably buffered, is rather large and cumbersome and therefore must necessarily be located in a "dedicated" area, normally at the top or at the bottom of the area occupied by the matrix of cells.
By contrast, a dedicated "select-line" decoding circuitry (first-level decoding) is usually placed at the beginning of each selection line (at least one for each NAND parcel of cells) and is reserved exclusively for the selection of the so-called select-lines.
If the memory matrix includes a large number of NAND parcels of cells (as in large memories, e.g. 128 parcels for a megabit memory), the load of the drivers of the single decoder for homonymous rows of all the NAND parcels is very large, and therefore the switching time becomes rather long. An excessively long wordline selection time of the memory has a negative influence on the access time of the memory device.
Moreover, the simultaneous switching of so many wordlines increases the power consumption, due to capacitive charging and discharging. This power consumption becomes larger the higher is the operating frequency of the memory device.
In addition, the switching of very large capacitances may cause non-negligible fluctuations on the supply rails V.sub.CC and V.sub.SS (ground), as well as inducing noise in sensitive circuits, such as for example sense amplifiers, reference systems, input circuits and the like. This worsens the overall performance of the device.
The disclosed innovations provide a decoder for NAND-type ROM devices which is compatible with a very small cell pitch of NAND-configured memory architectures, and which at the same time would permit to implement independent driving circuit for less than all of wordlines (rows) of the memory matrix, in order to avoid a drop of performance due to the above-identified effects of known row decoders utilized in this type of memory devices, is fulfilled by the present invention.
The decoder architecture provided by the present invention has an architecture based on four distinct selectors for implementing the required two-level decoding. These four selectors are driven through five distinct multiwire buses, coming from a pre-decoding circuitry, in accordance with common techniques which are well known to any skilled technician. In particular, a first block-selector is driven through two of said buses.